A manufacturing process of a SiC-metal-oxide-semiconductor field-effect transistor (MOSFET) in a case of using silicon carbide as a semiconductor will be described below.
First, in a unit cell portion, an n-type source implantation region is formed on a surface layer of a p-type well implantation region. Then, a gate oxide film is formed at least on an upper surface of the p-type well implantation region sandwiched between the n-type source implantation region and an n-type epitaxial layer.
Meanwhile, in a termination region, a field oxide film is formed on an upper surface of the p-type well implantation region. Then, a gate oxide film is formed on an upper surface of the field oxide film.
Then, in the unit cell portion, a gate conductive film made of polysilicon or the like is patterned to be formed on an upper surface of the gate oxide film. Further, in the termination region, a gate wire for making a contact with the gate conductive film and a front-surface electrode to be described later in the unit cell portion of the transistor is patterned to be formed on the upper surface of the gate oxide film.
After that, in the unit cell portion, an entire upper surface of the gate conductive film is subjected to cap oxidation to form a thermal oxide film. Then, a CVD oxide film, which is formed with a chemical vapor deposition (CVD) method, covering an upper surface of the thermal oxide film and a side surface of the gate conductive film is formed.
Meanwhile, in the termination region, an upper surface of the gate wire is oxidized to form a thermal oxide film. Then, a CVD oxide film covering an upper surface of the thermal oxide film and a side surface of the gate wire is formed.
Here, in the unit cell portion, the thermal oxide film formed to cover the gate conductive film and the CVD oxide film covering the upper surface of the thermal oxide film and the side surface of the gate conductive film are collectively referred to as an interlayer insulation film in the unit cell portion. A film thickness of the interlayer insulation film in the unit cell portion on the upper surface of the gate conductive film is a thickness obtained by adding together a film thickness of the thermal oxide film and a film thickness of the CVD oxide film.
Further, in the termination region, the thermal oxide film formed to cover the gate wire and the CVD oxide film covering the upper surface of the thermal oxide film and the side surface of the gate wire are collectively referred to as an interlayer insulation film in the termination region. A film thickness of the interlayer insulation film in the termination region on the upper surface of the gate wire is a thickness obtained by adding together a film thickness of the thermal oxide film and a film thickness of the CVD oxide film.
Next, in the unit cell portion, a source contact is opened in the CVD oxide film. Then, in order to reduce contact resistance, a silicide is formed in the source contact region. Further, in the termination region, a gate contact is opened in the interlayer insulation film.
Next, the front-surface electrode covering the source contact region and the gate contact region is formed.
Here, to make an ohmic contact with a silicide of Ni and SiC, i.e., NiSi, high temperature annealing of approximately 1000° C. needs to be performed after depositing Ni.
However, when the silicide is formed in the source contact region in the unit cell portion while the gate contact region is formed in the termination region, the gate wire made of polysilicon or the like in the termination region may abnormally grow due to reaction with Ni at a high temperature of approximately 1000° C. In such a case, polysilicon of the gate wire in the termination region is eliminated.
Accordingly, when the silicide is formed in the source contact region, the interlayer insulation film in the termination region needs to be reserved without forming the gate contact region such that a silicide is not formed in the gate contact region.
Therefore, in the manufacturing process of the SiC-MOSFET, for example, as illustrated in Patent Document 1, first, only the source contact region is opened in the unit cell portion to form a silicide in the region, and then the gate contact region is formed.